Translating network models to parallel hardware in NEURON

Abstract

The increasing complexity of network models poses a growing computational burden. At the same time, computational neuroscientists are finding it easier to access parallel hardware, such as multiprocessor personal computers, workstation clusters, and massively parallel supercomputers. The practical question is how to move a working network model from a single processor to parallel hardware. Here we show how to make this transition for models implemented with NEURON, in such a way that the final result will run and produce numerically identical results on either serial or parallel hardware. This allows users to develop and debug models on readily available local resources, then run their code without modification on a parallel supercomputer.

Figure 2.2.1

A NetCon attached to the presynaptic neuron PreCell detects spikes at the location labeled source, and delivers events to the synapse target which is attached to the postsynaptic neuron PostCell.

Figure 2.2.2

A presynaptic spike source PreCell with gid = 7 is on host 2, but its target is a synapse attached to PostCell on host 4. If PreCell spikes, a message is passed to all hosts so that NetCons that have gid 7 as their source will deliver events to their targets.

Fig. 3.1

Fig. 3.1. A network of 20 ball and stick cells arranged in a ring. Each cell i makes an excitatory synaptic connection to the middle of the dendrite of cell i+1, except for cell 19 which projects back to cell 0.

Fig. 3.2

Left: A ball and stick model cell driven by an excitatory synapse at the middle of its dendrite. Right: Effects of weak and strong synaptic inputs on membrane potential v observed at the junction of the dendrite and soma, where a NetCon is attached whose threshold is 10 mV (dashed line). The strong input elicits a spike, making v cross the NetCon’s threshold in a positive-going direction (arrow) so that an event will be sent to the NetCon’s target.