Solution-processable organic semiconductors are central to developing viable printed electronics, and performance comparable to that of amorphous silicon has been reported for films grown from soluble semiconductors. However, the seemingly desirable formation of large crystalline domains introduces grain boundaries, resulting in substantial device-to-device performance variations. Indeed, for films where the grain-boundary structure is random, a few unfavourable grain boundaries may dominate device performance. Here we isolate the effects of molecular-level structure at grain boundaries by engineering the microstructure of the high-performance n-type perylenediimide semiconductor PDI8-CN2 and analyse their consequences for charge transport. A combination of advanced X-ray scattering, first-principles computation and transistor characterization applied to PDI8-CN2 films reveals that grain-boundary orientation modulates carrier mobility by approximately two orders of magnitude. For PDI8-CN2 we show that the molecular packing motif (that is, herringbone versus slip-stacked) plays a decisive part in grain-boundary-induced transport anisotropy. The results of this study provide important guidelines for designing device-optimized molecular semiconductors.