100-Gbps CMOS transceiver for multilane optical backplane system with a 1.3 cm2 footprint

Opt Express. 2011 Dec 12;19(26):B777-83. doi: 10.1364/OE.19.00B777.


A compact 4 × 25 Gbps optical transceiver has been fabricated for an optical backplane system, which consists of a 4 × 25 Gbps DFB-LD array, a 4 × 25 Gbps PIN-PD array, and a CMOS transceiver chip. These are directly mounted on 9 × 14 mm(2) multi-layer ceramic package with an electromagnetic shield structure to suppress inner-channel crosstalk effectively. The transceiver includes an analog front-end as well as an electrical interface function to interface with the switch LSI or CPU. Power consumption was as low as 20 mW/Gbps, and a transmission experiment was successfully conducted at 25 Gbps.

Publication types

  • Research Support, Non-U.S. Gov't