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Source-gated Transistors for Order-Of-Magnitude Performance Improvements in Thin-Film Digital Circuits

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Source-gated Transistors for Order-Of-Magnitude Performance Improvements in Thin-Film Digital Circuits

R A Sporea et al. Sci Rep.

Abstract

Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.

Figures

Figure 1
Figure 1. Source-gated transistor operation.
(a) Cross-section of the fabricated polysilicon source-gated transistor, showing device structure, design parameters, current paths and depletion envelope at the source under small drain bias; (b) Measured output characteristics of a poly-Si SGT, showing very low dVSAT/dVG and flat saturated curves. d = 6 μm, S = 4 μm, W = 50 μm; (c) Simulation based on the fabricated polysilicon devices. The effectiveness of the field plate increases as it is brought closer to the semiconductor and the curve becomes much flatter between VSAT1 and VSAT2, allowing high gain to be available from very low drain voltage; (d) Measured transfer characteristics for a FET and SGT of the same geometry as (b) in polysilicon at VD = 5 V. The SGT curve can be tuned by barrier engineering; (e) SGT modeling agrees well with experiment.
Figure 2
Figure 2. Source gated transistors as building-blocks for inverters.
(a) Schematic showing circuit setup and node names; d.c. simulations were performed on the circuit in the dotted area; the whole circuit was used for transient; (b) Complementary inverter transfer plot (sketch). For best noise immunity and robustness, |Avmax|, VOH and VIL should be increased and VOL and VIH, reduced; (c) SGT inverter with resistive load showing agreement between simulation and experiment; (d) Simulated transfer characteristics of n- and p-type SGTs with different source barrier heights. The curves are identified by the chosen source metal work function, which directly relates to the effective height of the source barrier. For very low barriers, both the n- and the p-type devices behave as FETs and the source barrier does not play a role. Source metals can be chosen such that the on-current of both n- and p-type devices which form an inverter is roughly similar. This ensures that the tripping voltage is in the middle of the supply range when n- and p-type devices are of the same width. (e) Simulated transfer curves for FET and SGT complementary inverters in polysilicon. Owing to low saturation voltage and flat saturated characteristics, the SGT circuit responds closer to ideal than the FET version, particularly as the FET curves are suffering from kink effect at supply voltages as low as VDD = 5 V; (f) Comparison between FET and SGT inverters at lower supply voltages, VDD = 1 V and 2 V; (g) magnified overlay of the transfer characteristics of FET, SGT and mixed pFET/nSGT CMOS inverters at VDD = 2 V – for the mixed circuit, WSGT = 10 μm and WFET = 1 μm to account for the lower current obtained from the source-barrier limited SGT.
Figure 3
Figure 3. SGT inverter performance: gain and noise margin.
(a) Inverter gain is substantially higher in the SGT inverter. At low VDD, this advantage diminishes slightly as the transistors operate in a regime which is less controlled by the barrier and more FET-like (Fig. 1d); (b) D. C. noise margin (as defined in Fig. 2b) for SGT and FET inverters at different supply voltages. At high VDD the FET suffers from kink effect. At low VDD, the SGT operates in a region of its transfer characteristic which is less controlled by the source barrier and thus more FET-like.
Figure 4
Figure 4. Inverter power consumption and switching behavior.
(a) Current consumption during a d.c. switching cycle for SGT and FET inverters without a load. The current in the SGT circuit is controlled by the source contacts and thus lower than in the FET circuit, leading to a larger time constant and reduced operating speed; (b) Transient current in transistor M1 (Fig. 2a). The input waveform is given for reference. Highlighted areas are proportional to energy dissipated in one switching cycle (power-delay product – PD = VDD · ID · tclock). The SGT switches slower but draws considerably less current leading to somewhat improved PD; (c) Transient node voltages for the SGT circuit in Figure 2 and driven with a square wave. Attainable speed is in the MHz range.

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