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An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

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An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis

Fanny Spagnolo et al. Sensors (Basel).

Abstract

Connected Component Analysis (CCA) plays an important role in several image analysis and pattern recognition algorithms. Being one of the most time-consuming tasks in such applications, specific hardware accelerator for the CCA are highly desirable. As its main characteristic, the design of such an accelerator must be able to complete a run-time process of the input image frame without suspending the input streaming data-flow, by using a reasonable amount of hardware resources. This paper presents a new approach that allows virtually any feature of interest to be extracted in a single-pass from the input image frames. The proposed method has been validated by a proper system hardware implemented in a complete heterogeneous design, within a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) System on Chip (SoC) device. For processing 640 × 480 input image resolution, only 760 LUTs and 787 FFs were required. Moreover, a frame-rate of ~325 fps and a throughput of 95.37 Mp/s were achieved. When compared to several recent competitors, the proposed design exhibits the most favorable performance-resources trade-off.

Keywords: FPGAs; connected component analysis; embedded systems; features extraction.

Conflict of interest statement

The authors declare no conflict of interest.

Figures

Figure 1
Figure 1
Pixel connectivity for a four-connected (a) and an eight-connected (b) set.
Figure 2
Figure 2
A 4-connected (a) and an 8-connected (b) neighborhood for raster scan-based CCL.
Figure 3
Figure 3
Labeling process for a U-shaped connected component.
Figure 4
Figure 4
Labeling process for a more complex connected component.
Figure 5
Figure 5
Example of the chain of collisions solved by the backward merging technique.
Figure 6
Figure 6
Pseudo-code of the proposed labeling technique.
Figure 7
Figure 7
(a) The input binary image labeled by the novel algorithm. Status evolution of the Translator LUT and Feature Table (bf).
Figure 8
Figure 8
Sample images used to extract: (a) area features, (b) bounding boxes, and centroids.
Figure 9
Figure 9
Top-level architecture of the proposed CCA accelerator.
Figure 10
Figure 10
Design of the Decision module.
Figure 11
Figure 11
Design of the Extract Feature module.
Figure 12
Figure 12
Integrating the proposed CCA accelerator within modern heterogeneous FPGA-based SoCs.
Figure 13
Figure 13
Comparison of the resource efficiencies.
Figure 14
Figure 14
Sample test image.
Figure 15
Figure 15
Number of provisional labels assigned by the proposed algorithm to the examined image dataset.

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References

    1. Farhat W., Faiedg H., Souani C., Besbes K. Real-time embedded system for traffic sign recognition based on ZedBoard. J. Real Time Image Process. 2017:1–11. doi: 10.1007/s11554-017-0689-0. - DOI
    1. Lee S., Kim H., Sa J., Park B., Chung Y. Real-Time processing for intelligent surveillance applications. IEICE Electron. Express. 2017;14:20170227. doi: 10.1587/elex.14.20170227. - DOI
    1. Ronsen C., Denjiver P.A. Connected Components in Binary Images: The Detection Problem. Research Studies Press; New York, NY, USA: 1984.
    1. He L., Ren X., Gao Q., Zhao X., Yao B., Chao Y. The connected-component labeling problem: A review of state-of-the-art algorithms. Pattern Recognit. 2017;70:25–43. doi: 10.1016/j.patcog.2017.04.018. - DOI
    1. Sutheebanjard P., Premchaiswadi W. Efficient scan mask techniques for connected components labeling algorithm. EURASIP J. Image Video Process. 2011;2011:14. doi: 10.1186/1687-5281-2011-14. - DOI
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