A 4.8 ps root-mean-square resolution time-to-digital converter implemented in a 20 nm Cyclone-10 GX field-programmable gate array

Xin Yu; Haojie Xia; Weishi Li; Jin Zhang; Songtao Chang

doi:10.1063/5.0090783

A 4.8 ps root-mean-square resolution time-to-digital converter implemented in a 20 nm Cyclone-10 GX field-programmable gate array

Rev Sci Instrum. 2022 Aug 1;93(8):085001. doi: 10.1063/5.0090783.

Authors

Xin Yu¹, Haojie Xia¹, Weishi Li¹, Jin Zhang¹, Songtao Chang¹

Affiliation

¹ Anhui Province Key Laboratory of Measuring Theory and Precision Instrument, School of Instrument Science and Optoelectronics Engineering, Hefei University of Technology, Hefei 230009, Anhui, China.

PMID: 36050100
DOI: 10.1063/5.0090783

Abstract

It is difficult to improve the resolution and precision of a field-programmable gate array (FPGA)-based time-to-digital converter (TDC) in time interval measurement. In this study, we design a carry-look-ahead delay chain structure and integrate an interleaved sampling method with an online calibration and bin readjustment approach to implement a TDC. We take advantage of the adaptive logic module units applied in a Cyclone-10 GX (10CX220YF780E5G), which is a 20 nm low-power consumption and low-cost FPGA. In this new generation FPGA, we implemented a high-precision time interval measurement, which exceeded all our previous works with a 4.8 ps root-mean-square resolution and a 5.68 ps least-significant-bit resolution.