A flexible dual-gate hetero-synaptic transistor for spatiotemporal information processing

Abstract

Artificial synapses based on electrolyte gated transistors with conductance modulation characteristics have demonstrated their great potential in emulating the memory functions in the human brain for neuromorphic computing. While previous studies are mostly focused on the emulation of the basic memory functions of homo-synapses using single-gate transistors, multi-gate transistors offer opportunities for the mimicry of more complex and advanced memory formation behaviors in biological hetero-synapses. In this work, we demonstrate an artificial hetero-synapse based on a dual-gate electrolyte transistor that can implement in situ spatiotemporal information integration and storage. We show that electric pulses applied on a single gate or unsynchronized electric pulses applied on dual gates only induce volatile conductance modulation for short-term memory emulation. In contrast, the device integrates the electric pulses coincidently applied on the dual gates in a supralinear manner and exhibits nonvolatile conductance modulation, enabling long-term memory emulation. Further studies prove that artificial neural networks based on such hetero-synaptic transistors can autonomously filter the random noise signals in the dual-gate inputs during spatiotemporal integration, facilitating the formation of accurate and stable memory. Compared to the single-gate synaptic transistor, the classification accuracy of MNIST handwritten digits using the hetero-synaptic transistor is improved from 89.3% to 99.0%. These findings demonstrate the great potential of multi-gate hetero-synaptic transistors in simulating complex spatiotemporal information processing functions and provide new platforms for the design of advanced neuromorphic computing systems.

Fig. 1. (a) Schematic of a biological hetero-synapse with two presynaptic terminals and a postsynaptic terminal. (b) Schematic of a dual-gate electrolyte gated transistor. (c) Optical image of the P3HT based dual-gate electrolyte gated transistor. The channel length is 100 μm. Scale bar: 500 μm. (d) Transfer characteristic curve of the transistor measured during gate voltage sweeping. (e) Output characteristic curves of the transistor at different gate voltages. (f) Raman spectra of the P3HT channel film before and after gate voltage application. (g) Scheme showing a bent electrolyte gated transistor. (h) The channel current of the device in response to an electric pulse with varying amplitude at different bending states. (i) The channel current as a function of the pulse width for the device at different bending states.

Fig. 2. (a) Schematic showing the electrostatic ion modulation of the channel layer in the electrolyte gated transistor under single-terminal voltage gating. (b) A typical EPSC obtained in the electrolyte gated transistor triggered by an electric pulse (−1.2 V and 100 ms). (c) EPSCs triggered by a pair of electric pulses with a time interval of 500 ms. A₁ and A₂ represent the current intensity after the first and second pulse stimulations, respectively. Inset: PPF index as a function of pulse interval (Δt); the curve is fitted with an exponential decay function. (d) EPSCs excited by five electric pulses (−1.2 V and 100 ms) with different frequencies. (e) Peak postsynaptic current and peak variation (A_t–A₁) as a function of the pulse frequency in (d). (f) EPSCs excited by electric pulses (−1.4 V, 0.5 s) with different pulse numbers. (g) Peak current and peak current difference (A_t–A₁) as a function of pulse number in (f).

Fig. 3. (a) Illustration of a hetero-synapse excited by electric inputs transmitted by two presynaptic terminals and the resulting EPSC as an output. (b) Schematic showing the electrochemical ion modulation of the channel layer in the transistor under dual-terminal voltage gating. (c) EPSCs excited by the presynaptic spike (−1.2 V and 100 ms) separately/simultaneously applied on G₁ and G₂. (d) EPSCs excited by five presynaptic spikes (−1.2 V, 100 ms, and 3.3 Hz) separately/simultaneously applied on G₁ and G₂. (e) The measured sum (MS) current plotted as a function of the expected sum (ES) current. (f) Time-dependent device current under different stimuli conditions.

Fig. 4. (a) Illustration of a hetero-synapse performing spatiotemporal signal integration and memorization. Noise signals are introduced during the transmission of the original signals. (b) Examples of two noisy images separately delivered to the dual-gate hetero-synaptic transistor for processing. (c) The image stored in the dual-gate hetero-synaptic transistor after processing. (d) Illustration of a neural network based on the hetero-synaptic transistor for MNIST image recognition. (e) Comparison of the classification accuracy for the networks based on the dual-gate hetero-synaptic transistor and the single-gate homo-synaptic transistor.