Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS2 transistors

John Daniel; Zheng Sun; Xuejian Zhang; Yuanqiu Tan; Neil Dilley; Zhihong Chen; Joerg Appenzeller

doi:10.1038/s41467-024-48152-0

Experimental demonstration of an on-chip p-bit core based on stochastic magnetic tunnel junctions and 2D MoS₂ transistors

Nat Commun. 2024 May 15;15(1):4098. doi: 10.1038/s41467-024-48152-0.

Authors

John Daniel^{1

2}, Zheng Sun^{3

4}, Xuejian Zhang^{3

4}, Yuanqiu Tan^{3

4}, Neil Dilley³, Zhihong Chen^{3

4}, Joerg Appenzeller^{5

6}

Affiliations

¹ Birck Nanotechnology Center, Purdue University, West Lafayette, IN, 47907, USA. danie110@purdue.edu.
² Department of Physics and Astronomy, Purdue University, West Lafayette, IN, 47907, USA. danie110@purdue.edu.
³ Birck Nanotechnology Center, Purdue University, West Lafayette, IN, 47907, USA.
⁴ School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, USA.
⁵ Birck Nanotechnology Center, Purdue University, West Lafayette, IN, 47907, USA. appenzeller@purdue.edu.
⁶ School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, USA. appenzeller@purdue.edu.

Abstract

Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide-semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS₂ field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint.