Monolayer graphene has emerged as a key component of next-generation optoelectronic memory owing to its ultra-thin nature and seamless integration with silicon-based technology platform. However, the requirement of high erasing voltage, remains a significant hurdle. This can be accounted for by the charge trapping/de-trapping operation strategy of current heterostructure design, which results in less practicality and infeasibility for nonvolatile memory technology. In this work, a giant leap in erasing voltage down to -12 V and high on/off ratio of 8.2 × 106 under the low biases is revealed, originating from the mediation of interfacial dipolar coupling between 0D carbon quantum dots (CQDs) and 2D fluorine-functionalized graphene (f-Gra). Such 0D/2D interfacial circumstance, rather than intuitive charge transfer, introduces confined potential wells that immobilize the electrons: at adjacent CQDs the conduction-band offset prevents the electrons from returning to unoccupied valence states of CQDs, and near f-Gra the insulating F─C bonds negate further electron transport. Investigations on visualizing the interfacial physics of 0D/2D carbon-based designs, underscoring the performance improvement based on post anneal treatment, and unveiling the ternary buffering functionality in optical-signal processing, are anticipated to pave the keen step for the strategical designs of advanced optoelectronics.
Keywords: Raman mapping; heterostructure; interface dipole; low‐dimensional materials; optoelectronic memory.
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