We present the first fully integrated implementation of a patch-clamp measurement system with series-access resistance and parasitic capacitive compensation capability. The system was implemented in a 0.5- mum silicon-on-sapphire process and is capable of recording cell membrane currents up to plusmn20 nA, with an rms noise of 5 pA at 10-kHz bandwidth. The system can compensate for the capacitance and resistance of the electrode, up to 20 pF and up to 70% of the series-access resistance, respectively. The die size is 1150 by 700 mum. The power consumption is 300 muW at 3.3 V. The integrated patch-clamp system will be used to fabricate high-throughput planar patch-clamp systems.